This invention relates to a method of manufacturing a semiconductor device, such as, a DRAM (Dynamic Random Access Memory).
A DRAM (Dynamic Random Access Memory) generally includes a memory cell array in which a plurality of memory cell portions are arranged in a matrix form. Each of the memory cell portions is composed of a pair of memory cells. Herein, each of memory cells is structured by one selection MOS transistor (Metal Oxide Semiconductor) and one capacitor for storing electric charge.
In this case, the selection MOS transistor has a source region, a drain region and a gate electrode. With this structure, the source region or the drain region is coupled to the capacitor. Further, the gate electrodes of the MOS transistors constitute the respective word lines in each memory cell portion.
Moreover, the source region or the drain region is coupled to a bit line. Herein, it is to be noted that the source region or the drain region is formed as a diffusion layer in a semiconductor substrate.
Recently, the semiconductor device has been largely reduced in both size and integration. Consequently, the semiconductor device, in which design minimum dimension of a space between wiring lines is less than 0.2 .mu.m, has been fabricated.
The DRAM having capacity of 1 Gb has been manufactured by the use of such a fine processing technique. In such a DRAM, the known COB (Capacitor over Bit-line) structure has been often adopted in order to obtain high storing capacitance of the capacitor in a limited area. In this event, the capacitor is placed over the bit line in the COB structure.
Herein, disclosure has been made about the above-mentioned COB structure in Japanese Unexamined Patent Publication (JP-A) No. Hei. 3-174766, as illustrated in FIG. 1.
In FIG. 1, a plurality of word lines 4 are arranged in a vertical direction while a plurality of bit lines 10 are arranged in a parallel direction. In this case, the word lines 4 and the bit lines 10 are crossed to each other. In this event, each of the word lines 4 is composed of the gate electrode while each of the bit lines 10 is composed of the source region or the drain region, as mentioned before.
In such a DRAM of the COB structure, capacitor contacts 11 are placed between adjacent word lines 4, as illustrated in FIG. 1. The capacitor is connected to one of the source region and the drain region via the capacitor contact 11. On the other hand, the bit line 10 is connected to another one of the source region and the drain region via a bit contact 9.
Herein, it is to be noted that the reference numeral 3 denotes an impurity diffusion region which forms the source region or the drain region placed in the semiconductor substrate.
However, when the space between the wiring lines (namely, the space between the word lines 4) has been reduced, alignment margin becomes small.
In consequence, insulation between the wiring line (word line) 4 and the capacitor contact 11 can not be sufficiently ensured. To this end, a variety of methods have been adopted to ensure the insulation between the wiring line and the contact.
In FIG. 1, a connection pad 16 is arranged for each of the source region and the drain region. Thereby, the alignment margin between the word line (gate electrode) 4 and the capacitor contact 11 becomes large.
Subsequently, description has been made about a method of fabricating the connection pad 16 in FIGS. 2A through 2C. Herein, this method is also disclosed in above-mentioned Japanese Unexamined Patent Publication (JP-A) No. Hei. 3-174766.
Device isolation oxide films 2 and selection MOS transistors are first formed in a semiconductor substrate 1, as illustrated in FIG. 2A. In this event, each of the MOS transistors includes impurity diffusion regions 3 (source regions and drain a regions) which are formed in the semiconductor substrate 1, a gate electrode (word line) 4 which is formed via a gate insulating film between the source region and the drain region, and an insulating film 5 which covers the gate insulating film and the gate electrode 4.
In this state, an interlayer insulating film 6 is deposited on the semiconductor substrate 1. Thereafter, contact holes 7 are opened in the interlayer insulating film 6 in order to reach the impurity diffusion regions 3 as the source region and the drain region.
In this case, the contact holes 7 are opened by the use of the known self-alignment process so as to be electrically insulated from the gate electrode 4.
Subsequently, the connection pads 16 are selectively grown in only the contact holes 7, as shown in FIG. 2B. Herein, it is to be noted that the connection pad 16 is formed by, for example, polysilicon or single crystal silicon.
In this time, the polysilicon is grown to a depth of the contact hole 7 or more. Thereby, the polysilicon overflows from the contact hole 7. As a result, a diameter of the upper portion of the connection pad 16 exceeds that of the contact hole 7.
Thereafter, an interlayer insulating film 6' is deposited thereon, as illustrated in FIG. 2C. Successively, contact holes, which reach the upper portions of the connection pads 16, opened.
Subsequently, the bit contact 9, the bit line 10 which is connected to the bit contact 9, and the capacitor contacts 11 are sequentially formed. Further, the capacitor, which is connected to the capacitor contacts 11, is formed so as to complete the DRAM.
In this event, the capacitor includes a capacitor lower portion electrode 12 which is connected to the capacitor contacts 11, a capacitor upper portion electrode 13, and an insulating film which is formed between the capacitor lower electrode 12 and the capacitor upper portion electrode 13.
In this method, an upper surface of the connection pad 16 becomes large. In consequence, the alignment margin for the gate electrode 4 also becomes high during opening the contact holes for forming bit contact 9 and the capacitor contact 11.
Next, description is made about another method of fabricating a connection pad as disclosed in Proc. IEEE 1996, H. Koga et. al., titled "A 0.23 .mu.m.sup.2 Double Self-Aligned Contact Cell for Gigabit DRAMs With a Ge-Added Vertical Epitaxial Si Pad", IEDM 96, pp. 589-592 in FIGS. 3A through 3C.
Device isolation oxide films 2 and selection MOS transistors are first formed on a semiconductor substrate 1, as illustrated in FIG. 3A. In this event, each of the MOS transistors includes impurity diffusion regions 3 (source and drain regions) which are formed in the semiconductor substrate 1, and a gate electrode (word line) 4 which is formed via a gate insulating film between the source region and the drain region on the semiconductor substrate 1.
Further, an insulating film 5, such as, a silicon oxide film or a silicon nitride film are formed on an upper portion and a sidewall of the gate electrode 4. The insulating film 5, which covers the sidewall of the gate electrode 4, is formed by the use of the known anisotropic dry etching.
Immediately after the insulating films 5 are formed, the impurity diffusion regions 3 for forming the source region and the drain region of the MOS transistor are exposed for gate electrode 4 in the self-alignment manner.
Subsequently, for example, polysilicon is grown on only the silicon exposed portion (namely, the impurity diffusion region) to form a connection pad 16-2, as illustrated in FIG. 3B. In this event, no polysilicon is grown on the insulating film 5, such as, the silicon oxide film or the silicon nitride film.
The polysilicon is grown with two steps. Namely, the anisotropic epitaxial growth is performed in a first step so that the adjacent connection pads 16-2 do not contact to each other.
In a second step, when a height of the connection pad 16-2 exceeds a height of the gate electrode 4, isotropic growth is carried out so as to enlarge the upper surface of the connection pad 16-2 as illustrated in FIG. 3B.
Thereafter, an interlayer insulating film 6 is deposited thereon, as illustrated in FIG. 3C. Successively, contact holes, which reach the upper portions of the connection pads 16-2, opened.
Subsequently, the bit contact 9, the bit line 10 which is connected to the bit contact 9, and the capacitor contacts 11 are sequentially formed. Further, the capacitor, which is connected to the capacitor contacts 11, is formed to complete the DRAM.
In this event, the capacitor includes a capacitor lower portion electrode 12 which is connected to the capacitor contacts 11, a capacitor upper portion electrode 13, and an insulating film which is formed between the capacitor lower electrode 12 and the capacitor upper portion electrode 13.
The above-mentioned conventional methods have the following problems.
Namely, the silicon is selectively grown immediately after the contact hole 7 is opened in the method illustrated in FIG. 2. Consequently, the growth must be performed until the silicon overflows from the contact hole 7. As a result, duration for the selective growth becomes long.
In general, the selective growth of the silicon is carried out by utilizing difference of growth nucleus generation rate on the exposed surface. Under this circumstance, as the growth duration is longer, or a growth film thickness is thicker, selectivity of the growth becomes smaller.
Consequently, the adjacent connection pads 16 may contact to each other because the selectivity of the silicon growth is degraded in the method illustrated in FIG. 2.
Further, a complete clean surface of the silicon must be exposed on a bottom portion of the contact hole 7 in the above selective growth. However, it is difficult to obtain the complete clean surface on the bottom portion in fine contact hole 7 of 0.2 .mu.m or less.
On the other hand, when alignment tolerance (or alignment deviation) occurs between a pattern of the impurity diffusion region 3 and a pattern of the gate electrode 4 in the method illustrated in FIG. 3, as shown in FIG. 4, one side of the contact pads 16-2, which are connected to the capacitor contact 11, w may not be sufficiently grown. This is because the impurity diffusion region 3 is not sufficiently exposed due to the alignment tolerance (or deviation) of the gate electrode 4, and growth rate of the silicon becomes slow.
Moreover, the recent gate electrode 4 is generally formed by the double structure of silicide, such as, tungsten silicide or titanium silicide and polysilicon to reduce resistance thereof.
With this structure, when the contact hole is opened on the gate electrode 4, the silicide is exposed on a bottom portion thereof. However, it is difficult to selectively grow the silicon on the silicide. Under this circumstance, it is impossible to form the connection pad on the gate electrode.